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Section I · Quantum Technology

Quantum Computing Hardware Platforms: A Comparative Register

Four physical implementations of the qubit are assessed on the metrics that determine whether a machine can execute error-corrected algorithms of practical size.

Scope and methodology

This section compares superconducting transmon, trapped-ion, neutral-atom and photonic processors. Comparison is made on five bases: physical qubit count in the most recent peer-reviewed report, two-qubit gate fidelity, coherence or trap lifetime, gate duration, and demonstrated logical-qubit performance. Figures are drawn from journal publications and preprints. Vendor roadmaps are recorded in the Assessment but are not treated as evidence of capability.

Superconducting transmon processors

The transmon is a Josephson-junction circuit fabricated in aluminium on silicon or sapphire and operated near 15 mK inside a dilution refrigerator. Gate durations of 20 to 40 nanoseconds make it the fastest platform in the register. Google's 53-qubit Sycamore device executed a random circuit sampling task in 2019 that established the platform's capacity for large entangled circuits.1 In 2024 the 105-qubit Willow processor ran a distance-7 surface code at a logical error rate of 0.143 percent per cycle and recorded an error-suppression factor of approximately 2.14 when the code distance was raised from 5 to 7. This was the first demonstration of a memory operating below the fault-tolerance threshold.2

IBM's Heron r2 processor carries 156 qubits arranged in a heavy-hexagonal lattice with tunable couplers, and median two-qubit error near 3 × 10-3. The weaknesses of the platform are known: energy-relaxation times remain at the 60 to 300 microsecond level, connectivity is restricted to nearest neighbours, each qubit requires dedicated coaxial control lines that consume cryogenic cooling budget, and junction fabrication variability produces frequency collisions that must be tuned around.

Gold-plated stages and coaxial wiring of a dilution refrigerator that houses a superconducting quantum processor
Fig. 1. Dilution refrigerator infrastructure of the type used to hold transmon processors below 20 mK. Wiring and heat load scale with qubit count and constitute the dominant engineering constraint.

Trapped-ion systems

Trapped-ion processors encode qubits in the hyperfine or optical states of ytterbium-171, barium-137 or calcium-40 ions confined in radiofrequency Paul traps. Gates are driven by lasers or microwave fields. Quantinuum's H2 system, which uses a race-track trap and physically transports ions to bring arbitrary pairs into contact, reported two-qubit gate fidelities above 99.8 percent with all-to-all connectivity across 32 qubits at launch and 56 qubits in its 2024 upgrade.3

Coherence times measured in seconds to minutes give ions the largest ratio of coherence to gate time of any platform. The corresponding cost is speed: two-qubit gates take 10 to 100 microseconds, roughly three orders of magnitude slower than transmons, and ion transport adds further overhead. The number of ions that can be held in a single trap while preserving gate quality appears to saturate in the low hundreds, so scaling beyond that point depends on photonic interconnects between trap modules, which have been demonstrated at laboratory scale but not in a production system.

Neutral-atom and photonic approaches

Neutral-atom arrays

Rubidium or strontium atoms are held in arrays of optical tweezers and entangled through the Rydberg blockade. A Harvard, MIT and QuEra collaboration operated 280 physical qubits in 2023, encoded up to 48 logical qubits, and moved atoms during computation to achieve reconfigurable connectivity.4 Two-qubit fidelities near 99.5 percent have been reported. The principal limitation is cycle rate: array loading, imaging and atom loss constrain repetition to the hertz-to-kilohertz range, and atoms lost from the trap must be replaced between cycles.

Photonic processors

Photonic approaches encode information in squeezed states or single photons routed through integrated waveguides. Xanadu's Borealis machine performed Gaussian boson sampling across 216 squeezed-state modes in 2022.5 The platform operates at room temperature except for its detectors and is naturally suited to networking. Against this, entangling gates are probabilistic and photon loss compounds with circuit depth, so fault-tolerant proposals rely on generating large resource states and consuming them through fusion measurements, an architecture that PsiQuantum is pursuing in silicon photonics but which has not yet been demonstrated at logical-qubit scale.

Error correction and the threshold

The surface code, the leading error-correction scheme for planar architectures, tolerates physical error rates of order one percent and requires roughly a thousand physical qubits per logical qubit at the code distances needed for algorithms with 10-12 logical error budgets.6 Willow's result confirms that transmon error rates now sit below the threshold and that logical error falls with distance as theory predicts. The neutral-atom demonstration showed many logical qubits but did not show below-threshold scaling of a logical memory. Quantum low-density parity-check codes such as IBM's 144-qubit gross code, which encodes 12 logical qubits, promise roughly a tenfold reduction in overhead, but require long-range couplers that planar transmon chips do not yet provide.7

Comparative register

Table 1. Platform metrics from the most recent peer-reviewed reports.
PlatformLargest reported deviceTwo-qubit fidelityGate durationCoherence
Superconducting156 qubits (IBM Heron r2); 105 (Google Willow)99.7 – 99.9 %20 – 40 ns60 – 300 µs
Trapped ion56 qubits (Quantinuum H2)99.8 – 99.9 %10 – 100 µs> 1 s
Neutral atom280 qubits (Harvard / QuEra)≈ 99.5 %0.25 – 1 µs≈ 1 s
Photonic216 modes (Xanadu Borealis)ProbabilisticSub-nanosecondLoss-limited

Access and pricing

Cloud access is priced per task and per shot. Amazon Braket's published rate card lists IonQ Aria at USD 0.30 per task plus USD 0.03 per shot, Rigetti Ankaa at USD 0.30 per task plus USD 0.0009 per shot, and QuEra Aquila at USD 0.30 per task plus USD 0.01 per shot.8 IBM offers pay-as-you-go access to its utility-scale processors at USD 96 per minute of processor time, with premium plans negotiated for reserved capacity.9 A thousand-shot experiment on a 30-qubit circuit therefore costs between a few dollars and several tens of dollars depending on vendor, while an error-correction experiment of the Willow type, requiring millions of shots, would cost on the order of USD 104 to 105 at list price. On-premises systems are sold under individual agreements; installations of IBM System One machines exist in Germany, Japan, Canada and Spain.

Assessment

No platform has executed a fault-tolerant algorithm of commercial value. The field is in a period of logical-qubit demonstration in which each platform holds a distinct advantage.

  • Superconducting circuits lead on gate speed and are the only platform with a below-threshold memory demonstration; they trail on coherence and connectivity.
  • Trapped ions lead on fidelity and connectivity; they trail on speed and face a modular-scaling problem that is unsolved in production.
  • Neutral atoms lead on physical qubit count per unit cost and on reconfigurability; they trail on cycle rate and atom retention.
  • Photonics leads on room-temperature operation and networking; it trails on deterministic gate operation.

IBM's published roadmap places a 200-logical-qubit fault-tolerant system, designated Starling, in 2029, and Google's programme lists a long-lived logical qubit as its next milestone.10 These dates are recorded as stated. The register will be revised when either milestone is reported in the peer-reviewed literature.

References

  1. Arute, F. et al. "Quantum supremacy using a programmable superconducting processor." Nature 574, 505–510 (2019). doi:10.1038/s41586-019-1666-5 ↩
  2. Google Quantum AI and Collaborators. "Quantum error correction below the surface code threshold." Nature 638, 920–926 (2025); preprint arXiv:2408.13687. ↩
  3. Moses, S. A. et al. "A Race-Track Trapped-Ion Quantum Processor." Physical Review X 13, 041052 (2023); preprint arXiv:2305.03828. ↩
  4. Bluvstein, D. et al. "Logical quantum processor based on reconfigurable atom arrays." Nature 626, 58–65 (2024). doi:10.1038/s41586-023-06927-3 ↩
  5. Madsen, L. S. et al. "Quantum computational advantage with a programmable photonic processor." Nature 606, 75–81 (2022). doi:10.1038/s41586-022-04725-x ↩
  6. Fowler, A. G., Mariantoni, M., Martinis, J. M. and Cleland, A. N. "Surface codes: Towards practical large-scale quantum computation." Physical Review A 86, 032324 (2012); preprint arXiv:1208.0928. ↩
  7. Bravyi, S. et al. "High-threshold and low-overhead fault-tolerant quantum memory." Nature 627, 778–782 (2024). doi:10.1038/s41586-024-07107-7 ↩
  8. Amazon Web Services. "Amazon Braket Pricing." aws.amazon.com/braket/pricing (accessed January 2026). ↩
  9. IBM. "IBM Quantum access plans and pricing." ibm.com/quantum/pricing (accessed January 2026). ↩
  10. IBM. "IBM Quantum Development and Innovation Roadmap." ibm.com/roadmaps/quantum (accessed January 2026). ↩